Stage 1 Loader 1.0.2.0 (build 42703)
Built: 2014-03-14 at 03:36:58

Secure Boot Enabled on the Processor

PRID: 000C1202
POWER ON RESET CFG:924C0FB2
Initialized I2C0 Controller.
Initialized I2C1 Controller.
SPD Rev:0x12 DIMM:0 Type:2 Speed:800MHz #Rank:1
DDR3: Node 0 Channel 0 Mem size = 4096 MB UDIMM
set freq:800000
DDR3: Node 0 DRAM frequency 800 MHz
DDR3: Node 0 CPU frequency 1600 MHz
mtb_ps:125 clock:1250 trc:39 trcd:11 trp:11
AP3:A0CFFF0 ODTP1:10000
Board DDR VDD set to 1.5V.
N:0 CH:0 additional rdlvl rdly:1
N:0 Ch:0 m:32 s:32 R OK.
Rank:0 HW WLVL Passed Mask:1FF
AP3:A0CFFF0 ODTP1:10000
n:0 ch:0 RTT WR:0200
===N:0 Ch:0 m:32 s:32 RW OK.
Starting address/cmd align [4T..3T]
N:0 CH:0 SR ADDR/CMD:(B:00 E:57 00) 2B
N:0 CH:0 MR ADDR/CMD:(00 7F 00) 3F
n:0 ch:0 addr mode:4T OK
N:0 CH:0 MR ADDR/CMD:(00 7F 00) 3F
n:0 ch:0 addr mode:3T OK
n:0 ch:0 addr mode:3T OK
Node:0 Ch:0 TGE Set Memory:4096 MB value:FF FF -- PASS
Node:0 Ch:0 TGE Set Memory:4096 MB value:FF 00 -- PASS
Node:0 Ch:0 TGE Set Memory:4096 MB value:AA 55 -- PASS
Node:0 Ch:0 TGE Set Memory:4096 MB value:00 00 -- PASS

DDR3 Initialization Passed.
Setup Interleave (node:0 chan:1)
NBU0 DRAM BAR0 base: 00000000 limit: 0013f000 xlate: 00000001 node: 00000000 (    0 MB ->   320 MB, size:   320 MB)
NBU0 DRAM BAR1 base: 001d0000 limit: 00bff000 xlate: 00090001 node: 00000000 (  464 MB ->  3072 MB, size:  2608 MB)
NBU0 DRAM BAR2 base: 00e00000 limit: 0128f000 xlate: 00290001 node: 00000000 ( 3584 MB ->  4752 MB, size:  1168 MB)
Hit any key to stop autoboot:  0

CPBoot image is signed
Verifying CPBoot checksum...
CPBoot check passed
Signer Cert OK
Policy Cert OK
RSA signature verified.
## Starting application at 0x8C100000 ...


CPBoot 1.0.0.0 (build 42703)
Built: 2014-03-14 at 03:17:55

DRAM:  4 GB
Detected [XLP208 Rev B0 (Secure Boot) ]
CPLD:  rev: 1.b (30:8000|32:0001|33:0000|34:0000|35:0000)
Flash: 32 MB
PCIE (B0:D01:F0) : No Link.
Bank:  Primary
Board: A7030
Proto: 2
CPU:   XLP208 Rev B0 (Secure Boot)
Clock: Core 1600 MHz / SoC 1600 MHz (924c0fb2)