Stage 1 Loader 1.0.6.0 (build 65676) Built: 2018-07-06 at 04:30:15 Secure Boot Enabled on the Processor Bank: Secondary Watchdog CPLD: rev: 3.0 (30:8008|32:0004|33:0000|34:0000|35:0000) Initialized I2C0 Controller. Initialized I2C1 Controller. SPD Rev:0x13 DIMM:0 Type:2 Speed:800MHz #Rank:1 DDR3: Node 0 Channel 0 Mem size = 2048 MB UDIMM SPD Rev:0x13 DIMM:0 Type:2 Speed:800MHz #Rank:1 DDR3: Node 0 Channel 1 Mem size = 2048 MB UDIMM SPD Rev:0x13 DIMM:0 Type:2 Speed:800MHz #Rank:1 DDR3: Node 0 Channel 2 Mem size = 2048 MB UDIMM SPD Rev:0x13 DIMM:0 Type:2 Speed:800MHz #Rank:1 DDR3: Node 0 Channel 3 Mem size = 2048 MB UDIMM Ref Clk @133MHz DDR3: Node 0 DRAM frequency 800 MHz DDR3: Node 0 CPU frequency 800 MHz mtb_ps:125 clock:1250 trc:39 trcd:11 trp:11 AP3:A0CFFF0 ODTP1:10000 Board DDR VDD set to 1.5V. N:0 CH:0 additional rdlvl rdly:1 N:0 Ch:0 m:32 s:32 R OK. Rank:0 HW WLVL Passed Mask:1FF AP3:A0CFFF0 ODTP1:10000 n:0 ch:0 RTT WR:0200 ===N:0 Ch:0 m:32 s:32 RW OK. Starting address/cmd align [4T..3T] N:0 CH:0 SR ADDR/CMD:(B:00 E:5A 00) 2D N:0 CH:0 MR ADDR/CMD:(00 7F 00) 3F n:0 ch:0 addr mode:4T OK N:0 CH:0 MR ADDR/CMD:(00 7F 00) 3F n:0 ch:0 addr mode:3T OK n:0 ch:0 addr mode:3T OK Node:0 Ch:0 TGE Set Memory:2048 MB value:FF FF -- PASS Node:0 Ch:0 TGE Set Memory:2048 MB value:FF 00 -- PASS Node:0 Ch:0 TGE Set Memory:2048 MB value:AA 55 -- PASS Node:0 Ch:0 TGE Set Memory:2048 MB value:00 00 -- PASS mtb_ps:125 clock:1250 trc:39 trcd:11 trp:11 AP3:A0CFFF0 ODTP1:10000 Board DDR VDD set to 1.5V. N:0 CH:1 additional rdlvl rdly:1 N:0 Ch:1 m:32 s:32 R OK. Rank:0 HW WLVL Passed Mask:1FF AP3:A0CFFF0 ODTP1:10000 n:0 ch:1 RTT WR:0200 DDR3: N:0 Ch:1 rank:0 write leveling done_mask:17F ERROR: DDR3 Leveling. n:0 ch:1 fail mask:00000002 =-=-=DDR3 DUMP BEGIN 0 1 MR0:1C71 BA:0 ppd:1 wr :6 dll:0 tm :0 cas:7 rbt:0 cl :0 bl :1 MR1:0216 BA:1 Qoff :0 TDQS :0 WLVL :0 RTT_NOM:1 0 1 DIC :0 1 DLL :0 MR2:0218 BA:2 RTT_WR:1 SRT :0 ASR :0 CWL :3 PASR :0 MR3:0000 BA:3 MPR:0 Addr:0 ZQL:0400 BA:0 ZQL:0400 BA:0 RDRD DF RANK: 0x00000003 RDWR SM RANK: 0x00000003 RDWR DF RANK: 0x00000003 WRRD DF RANK: 0x00000003 WRWR DF RANK: 0x00000003 WRRD SM RANK: 0x00000003 SMTY_SMRK_TA: 0x00000004 RDRD_DFRK_TA: 0x00000007 RDWR_SMRK_TA: 0x0000000a RDWR_DFRK_TA: 0x0000000a WRRD_DFRK_TA: 0x00000004 WRWR_DFRK_TA: 0x00000009 WRRD_SMRK_TA: 0x00000004 WRRD_SMRK_TA_LCL: 0x00000012 [000]:000301B9 SHADOWMR [001]:00000216 RK0SMR1 [002]:00000216 RK1SMR1 [003]:00000216 RK2SMR1 [004]:00000216 RK3SMR1 [005]:01000304 BP1 [006]:18050B27 BP2 [007]:0001031C BP3 [008]:18600080 BP4 [009]:04060B06 BP5 [00A]:03030303 BP6 [00B]:20010040 BP7 [00C]:0088200A BP8 [00D]:00861A80 BP9 [00E]:20027100 BP10 [00F]:000032C8 BP11 [010]:64081454 BP12 [011]:42000885 BP13 [012]:00000400 BP14 [013]:2507281F BP15 [014]:00030300 AP1 [015]:0F0A0703 AP2 [016]:0A0CFFF0 AP3 [017]:00010000 ODTP1 [018]:00000046 ODTP2 [019]:00000000 PZN1 [01A]:00000000 PZN2 [01B]:00000000 PZN3 [01C]:00000000 PZN4 [01D]:00000000 ECCLOG1 [01E]:00000000 ECCLOG2 [01F]:F8021821 DIS1 [020]:F8000031 DIS2 [021]:F8021611 DIS3 [022]:F81C7101 DIS4 [023]:5E040081 DIS5 [024]:AE040081 DIS6 [025]:FA040081 RFS1 [026]:F9000001 RFS2 [027]:0F000080 RFS3 [028]:0F000080 RFS4 [029]:FA040081 SRE1 [02A]:F1000001 SRE2 [02B]:0F000080 SRE3 [02C]:0F000080 SRE4 [02D]:5E000081 ZQC1 [02E]:AE000081 ZQC2 [02F]:F7000081 PDE1 [030]:07000080 PDE2 [031]:FF000081 PDX1 [032]:0F000080 PDX2 [033]:F8021821 UCS1 [034]:F8000031 UCS2 [035]:F8021611 UCS3 [036]:F81C7101 UCS4 [037]:5E040081 UCS5 [038]:AE040081 UCS6 [039]:00111502 DP1 [03A]:080A080A DP2 [03B]:091F210F DP3 [03C]:02040204 DP4 [03D]:10120704 DP5 [03E]:03641314 DP6 [03F]:070E0703 DP7 [040]:0A101008 DP8 [041]:1E092A18 DP9 [042]:0004001A DP10 [043]:241A0120 DP11 [044]:00008001 DP12 [045]:0E00185C DP13 [046]:260096A2 DP14 [047]:000445C0 DP15 [048]:201E1C00 NSL [049]:0004022F CM0 [04A]:10402090 CM1 [04B]:00000000 UCSC [04C]:0473F000 WLLIM [04D]:00000812 WLCTL [04E]:000000AA CST [04F]:00000000 GPCE [050]:00000000 PCC0 [051]:00000000 PCV0 [052]:00000000 PCC1 [053]:00000000 PCV1 [054]:00000000 PCC2 [055]:00000000 PCV2 [056]:00000000 PCC3 [057]:00000000 PCV3 [058]:01010101 TGED1 [059]:01010101 TGED2 [05A]:02020202 TGED3 [05B]:02020202 TGED4 [05C]:04040404 TGED5 [05D]:04040404 TGED6 [05E]:08080808 TGED7 [05F]:08080808 TGED8 [060]:10101010 TGED9 [061]:10101010 TGED10 [062]:20202020 TGED11 [063]:20202020 TGED12 [064]:40404040 TGED13 [065]:40404040 TGED14 [066]:80808080 TGED15 [067]:80808080 TGED16 [068]:01020408 TGECB1 [069]:10204080 TGECB2 [06A]:00000000 TGEA1 [06B]:00004000 TGEA2 [06C]:00000008 TGECNT [06D]:00000008 TGE_RDRETCNT [06E]:01010101 TGE_DMVECTLO [06F]:01010101 TGE_DMVECTHI [070]:00000000 TGE_CBMVECT [071]:00000001 TGECON [072]:00000000 SCR0 [073]:00000000 SCR1 [074]:00000000 SCR2 [075]:00000000 SCR3 [076]:000601E0 PRG DDR3 0.1: Address Mode : 4T (Addr Delay:3 AL:2 CS Delay:2) Additional RL Delay : 1 cycle(s) Single-Rank load DLL: 0x20/0x80 cycle Multi-Rank load DLL: 0x20/0x80 cycle Wr DQS pre-launch : 1 cycle(s) R0 WLV CDLY 03 03 03 03 02 02 02 06 03 R0 WLV FDLY 3E 2E 22 10 36 2A 1E 0E 02 R0 WPS DLY 00 00 00 00 00 00 00 00 00 R0 RLV CDLY 04 04 04 03 03 03 02 02 03 R0 RLV FDLY 14 0D 01 36 0F 01 39 29 2A R0 RBPS DLY 27 28 28 25 29 2A 26 21 27 DQS0_CALDLL_BASE = 0x000 DQS1_CALDLL_BASE = 0x040 DQS2_CALDLL_BASE = 0x080 DQS3_CALDLL_BASE = 0x0C0 DQS4_CALDLL_BASE = 0x100 DQS5_CALDLL_BASE = 0x140 DQS6_CALDLL_BASE = 0x180 DQS7_CALDLL_BASE = 0x1C0 DQS8_CALDLL_BASE = 0x200 MRCMD_CALDLL_BASE = 0x240, 005B 0BA0 7171 2A2C 0004 PAD0_CAL_BASE = 0x280, 1FC0 102F 0000 6280 0000 8CF1 0CF1 0000 PAD1_CAL_BASE = 0x2C0, 1FC0 102F 0000 8CB2 0000 8CB0 0CB0 0000 PAD2_CAL_BASE = 0x300, 1FC0 102F 0000 8CF3 0000 8CF1 0CF1 0000 SRCMD_CALDLL_BASE = 0x340, 005B 0BA0 7171 2A2C 0004 --------------------------------------------------- 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 --------------------------------------------------- 005E 005E 005C 005C 005C 005C 005C 005B 005E CALDLL_RES 0C20 0C20 0BA0 0BA0 0BA0 0BA0 0BA0 0BA0 0C20 SHR_TXPSDLL_CTRL 173E 112E 0C22 0610 13B6 0F2A 0B1E 050E 0082 RK0_TXWLDLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK1_TXWLDLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK2_TXWLDLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK3_TXWLDLL_CTRL 0794 050D 0081 13B6 058F 0081 14B9 0EA9 0FAA RK0_RXSEDLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK1_RXSEDLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK2_RXSEDLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK3_RXSEDLL_CTRL 0EA7 0EA8 0EA8 0DA5 0EA9 0F2A 0DA6 0BA1 0EA7 RK0_RXPSDLL_CTRL 0C20 0C20 0BA0 0BA0 0BA0 0BA0 0BA0 0BA0 0C20 RK1_RXPSDLL_CTRL 0C20 0C20 0BA0 0BA0 0BA0 0BA0 0BA0 0BA0 0C20 RK2_RXPSDLL_CTRL 0C20 0C20 0BA0 0BA0 0BA0 0BA0 0BA0 0BA0 0C20 RK3_RXPSDLL_CTRL 0000 000F 007F 0FFF FFF8 FFE0 FF00 F000 7FFF SHR_WLRSLT_DATA_LO FFFF FFF0 FF80 FC00 0003 001F 00FF 0FFF 8000 SHR_WLRSLT_DATA_HI FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF SHR_WLRSLT_VLD_LO FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF SHR_WLRSLT_VLD_HI FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF SHR_WLRSLT_PURE_LO FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF SHR_WLRSLT_PURE_HI 0008 0008 0008 0008 0008 0008 0008 0008 0008 SHR_WLED_CFG 80BC 80AC 80A0 708C 7034 5828 401C 810C 8080 SHR_WLED_FVR 4500 44B0 44A4 4494 4438 442C 4420 4510 4484 SHR_WLED_NVR 14BE 14AE 14A2 1490 1436 142A 141E 150E 1482 SHR_WLED_ALN 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ0_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ1_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ2_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ3_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ4_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ5_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ6_MICRODLL_CTRL 0000 0000 0000 0000 0000 0000 0000 0000 0000 DQ7_MICRODLL_CTRL 0003 0003 0003 0003 0002 0002 0002 0006 0003 RK0_TXWLDLY_SEL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK1_TXWLDLY_SEL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK2_TXWLDLY_SEL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK3_TXWLDLY_SEL 0010 0010 0010 0008 0008 0008 0004 0004 0008 RK0_RXSEDLY_SEL 0001 0001 0001 0001 0001 0001 0001 0001 0001 RK1_RXSEDLY_SEL 0001 0001 0001 0001 0001 0001 0001 0001 0001 RK2_RXSEDLY_SEL 0001 0001 0001 0001 0001 0001 0001 0001 0001 RK3_RXSEDLY_SEL 0005 0005 0005 0005 0005 0005 0005 0005 0005 RK0_RXDVDLY_SEL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK1_RXDVDLY_SEL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK2_RXDVDLY_SEL 0000 0000 0000 0000 0000 0000 0000 0000 0000 RK3_RXDVDLY_SEL 0004 0004 0004 0002 0002 0002 0001 0001 0002 RK0_CTENDLY_SEL 0001 0001 0001 0001 0001 0001 0001 0001 0001 RK1_CTENDLY_SEL 0001 0001 0001 0001 0001 0001 0001 0001 0001 RK2_CTENDLY_SEL 0001 0001 0001 0001 0001 0001 0001 0001 0001 RK3_CTENDLY_SEL 000A 000A 000A 000A 000A 000A 000A 000A 000A STRB_EN_SAMPLE 7171 7171 7171 7171 7171 7171 7171 7171 7171 PAD_DRV_SCALE 4040 4040 4040 4040 4040 4040 4040 4040 4040 PAD_TERM_SCALE 2B2D 2B2D 2B2D 2B2D 2B2D 2B2D 2B2D 2B2D 2B2D PAD_DRV_CTRL 191A 191A 191A 191A 191A 191A 191A 191A 191A PAD_TERM_CTRL =-=-=DDR3 DUMP END 0 1 XLOAD ERROR:-1 cpxload# ---------------------------------------------------------------------- cpxload# help barinit - barinit cmp - memory comparing cp - memory copy cpboot - execute CPBoot cpld - cpld : read/write CPLD registers cpu - cpu dfs div crc16 - compute crc16 ddr - show ddr registers ddrinit - ddrinit ddrrd - read ddr registers ddrwr - write ddr registers except - Exception Handler Test help - print command description/usage i2c - i2c access lcm - initialize the LCM loop - loop cmds md - memory display memecc - memecc memsi - full memory test mfcr - mfcr: rd registers mtcr - mtcr: write registers mtest - memory test mw - memory write (fill) phy - show ddr phy registers phyrd - read ddr phy registers phywr - write ddr phy registers printenv- print environment variables rd - rd registers reset - Perform RESET of the CPU rw - write registers spd - show ddr3 spd data sys - sys dfs div tge - tge cmds