Stage 1 Loader 1.0.5.0 (build 56553)
Built: 2016-09-22 at 05:02:10
Secure Boot Enabled on the Processor
Bank: Secondary Watchdog
CPLD: rev: 3.0 (30:0068|32:0004|33:0000|34:0000|35:0000)
PRID: 000C1203
POWER ON RESET CFG:30CC0FF2
Initialized I2C0 Controller.
Initialized I2C1 Controller.
SPD Rev:0x11 DIMM:0 Type:2 Speed:666MHz #Rank:1
DDR3: Node 0 Channel 0 Mem size = 4096 MB UDIMM
set freq:666666
DDR3: Node 0 DRAM frequency 666 MHz
DDR3: Node 0 CPU frequency 800 MHz
mtb_ps:125 clock:1500 trc:33 trcd:9 trp:9
AP3:A0CFFF0 ODTP1:10000
Board DDR VDD set to 1.5V.
N:0 CH:0 additional rdlvl rdly:1
N:0 Ch:0 m:32 s:32 R OK.
Rank:0 HW WLVL Passed Mask:1FF
AP3:A0CFFF0 ODTP1:10000
n:0 ch:0 RTT WR:0200
===N:0 Ch:0 m:32 s:32 RW OK.
Node:0 Ch:0 TGE Set Memory:4096 MB value:FF FF -- PASS
Node:0 Ch:0 TGE Set Memory:4096 MB value:FF 00 -- PASS
Node:0 Ch:0 TGE Set Memory:4096 MB value:AA 55 -- PASS
Node:0 Ch:0 TGE Set Memory:4096 MB value:00 00 -- PASS
DDR3 Initialization Passed.
NBU0 DRAM BAR0 base: 00000000 limit: 0013f000 xlate: 00000001 node: 00000000 ( 0 MB -> 320 MB, size: 320 MB)
NBU0 DRAM BAR1 base: 001d0000 limit: 00bff000 xlate: 00090001 node: 00000000 ( 464 MB -> 3072 MB, size: 2608 MB)
NBU0 DRAM BAR2 base: 00e00000 limit: 0128f000 xlate: 00290001 node: 00000000 ( 3584 MB -> 4752 MB, size: 1168 MB)
Hit Ctrl + X keys to stop autoboot: 0
CPBoot image is signed
Verifying CPBoot checksum...
CPBoot check passed
Signer Cert OK
Policy Cert OK
RSA signature verified.
## Starting application at 0x8C100000 ...
CPBoot 1.0.7.0 (build 56553)
Built: 2016-09-22 at 04:52:12
DRAM: 4 GB
Detected [XLP208 Rev B1 (Secure Boot) ] (6a|6a)
CPLD: rev: 3.0 (30:0068|32:0004|33:0000|34:0000|35:0000)
Flash: 16 MB
Watchdog caused the previous reset. So Running Watchdog Framework
Watchdog reset caused in cpboot context
-----------------------------------------------------------------
We even can not step in cpboot, we can go into cpxload only now. What can we do now ? We just upgrade from AOS6.5 to AOS8.2.1 why like this ?
cpxload# help
barinit - barinit
cmp - memory comparing
cp - memory copy
cpboot - execute CPBoot
cpld - cpld : read/write CPLD registers
crc16 - compute crc16
ddr - show ddr registers
ddrinit - ddrinit
ddrrd - read ddr registers
ddrwr - write ddr registers
except - Exception Handler Test
help - print command description/usage
i2c - i2c access
lcm - initialize the LCM
loop - loop cmds
md - memory display
memecc - memecc
memsi - full memory test
mfcr - mfcr: rd registers
mtcr - mtcr: write registers
mtest - memory test
mw - memory write (fill)
phy - show ddr phy registers
phyrd - read ddr phy registers
phywr - write ddr phy registers
printenv- print environment variables
rd - rd registers
rw - write registers
spd - show ddr3 spd data
tge - tge cmds
cpxload#
System will be rebooted in about 1 seconds...